//-------------------------------------------------------------------------------------------------
//`include "test_led_def.v"
//仿真单位/精度
`timescale 1ns/1ps
//-------------------------------------------------------------------------------------------------
module test_led (
input clk ,
output [7:0] ov_led
);
wire clk_10m;
wire clk_100m;
wire clk_ibufg;
wire dcm_reset;
wire dcm_lock;
wire clk_10m_reset;
reg [7:0] pwr_up_cnt =
8‘b0;
reg [21:0] led_cnt =
22‘b0;
reg [1:0] shift_reset
= 2‘b11;
reg [7:0] led_shift
= 8‘b00000001;
// ref
signals
// ref
ARCHITECTURE
//
===============================================================================================
//
//
===============================================================================================
//
-------------------------------------------------------------------------------------
// ibufg
//
-------------------------------------------------------------------------------------
IBUFG
IBUFG_inst (
.O (clk_ibufg ), //
Clock buffer output
.I (clk ) //
Clock buffer input (connect directly to top-level port)
);
//
-------------------------------------------------------------------------------------
// 上电复位dcm，时钟采用ibufg输出的时钟
//
-------------------------------------------------------------------------------------
always @
(posedge clk_ibufg) begin
if(pwr_up_cnt[7]
== 1‘b0) begin
pwr_up_cnt <=
pwr_up_cnt + 1‘b1;
end
end
assign dcm_reset
= !pwr_up_cnt[7];
//
-------------------------------------------------------------------------------------
// DCM
//
-------------------------------------------------------------------------------------
clk_wiz_v3_2
clk_wiz_v3_2_inst (
.CLK_IN1 (clk_ibufg ),
.CLK_OUT1 (clk_10m ),
.CLK_OUT2 (clk_100m ),
.RESET (dcm_reset ),
.LOCKED (dcm_lock )
);
//
-------------------------------------------------------------------------------------
// 10M时钟域的复位信号
//
-------------------------------------------------------------------------------------
always @
(posedge clk_10m or negedge dcm_lock) begin
if(!dcm_lock)
begin
shift_reset <=
2‘b11;
end
else
begin
shift_reset <=
{shift_reset[0],1‘b0};
end
end
assign clk_10m_reset =
shift_reset[1];
//
-------------------------------------------------------------------------------------
// 10M时钟域的计数器，共计数21次幂，每秒有5次的使能
//
-------------------------------------------------------------------------------------
always @
(posedge clk_10m) begin
if(clk_10m_reset)
begin
led_cnt <=
22‘b0;
end
else
begin
if(led_cnt[21]
== 1‘b1) begin
led_cnt <=
22‘b0;
end
else
begin
led_cnt <=
led_cnt + 1‘b1;
end
end
end
//
-------------------------------------------------------------------------------------
// led移位显示，每次只点亮一个led，1s移位5次
//
-------------------------------------------------------------------------------------
always @
(posedge clk_10m) begin
if(clk_10m_reset)
begin
led_shift <=
8‘b00000001;
end
else
begin
if(led_cnt[21]
== 1‘b1) begin
led_shift <=
{led_shift[6:0],led_shift[7]};
end
end
end
assign ov_led =
led_shift;
endmodule
## ===============================================================================================
## nexys3
## ucf
## ===============================================================================================
# ref 1 pin location
------------------------------------------------------------------------------
#----ref 时钟复位
---------------------------------------------------------------------------------
NET "clk" LOC
= "V10" | IOSTANDARD = "LVCMOS33"; #Bank = 2, pin name =
IO_L30N_GCLK0_USERCCLK, Sch name =
GCLK
#----ref FPGA测试信号
-----------------------------------------------------------------------------
NET "ov_led[0]" LOC =
"U16" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L2P_CMPCLK,
Sch name =
LD0
NET "ov_led[1]" LOC =
"V16" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L2N_CMPMOSI,
Sch name =
LD1
NET "ov_led[2]" LOC =
"U15" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L5P,
Sch name = LD2
NET "ov_led[3]" LOC =
"V15" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L5N,
Sch name = LD3
NET "ov_led[4]" LOC =
"M11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L15P,
Sch name = LD4
NET "ov_led[5]" LOC =
"N11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L15N,
Sch name = LD5
NET "ov_led[6]" LOC =
"R11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L16P,
Sch name = LD6
NET "ov_led[7]" LOC =
"T11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L16N_VREF,
Sch
name = LD7
# ref 2 timing constraints
------------------------------------------------------------------------
#----ref
时钟约束----------------------------------------------------------------------------------
NET "clk" TNM_NET = "TNM_clk";
TIMESPEC "TS_clk" = PERIOD "TNM_clk" 100 MHz;
#----ref MultiPath
约束----------------------------------------------------------------------------
#NET "clk_rst_top_inst/w_reset_loc_pll" TIG;
#NET "CLKA" TNM_NET = FFS "GRP_A";
#NET "CLKB" TNM_NET = FFS "GRP_B";
#TIMESPEC TS_Example = FROM "GRP_A" TO "GRP_B" 5 ns DATAPATHONLY;
实际测试，led1s移动5次，与设计的要求一致
