Verification之PSL之Quick guide

1 vunit name (hierarchical_HDL_design_unit)
2 {
3　　 default clock is <clock_decl>;
4 　　<PSL_stmts_and/or_HDL_decls_and_stmts>;
5 　　...
6 }

1 vunit check_dram_controller(dram_control(RTL))
2 {
3 　　default clock is rising_edge(clk);
4 　　sequence refresh_seq is {(cas and ras and we)[*2];   
5 　　(not cas and not ras)};
6 　　...
7 }