其实就是用验证平台代替板级验证。
we can instantiate a mem block in testbench and put a .mif file into the mem block. This .mif file is transferred from an image file by matlab or other exe. On the othe hand, Verilog bench can write processed data back into a .txt file, which can be transferred back into image by matlab or other exe.
By doing this, we no more need image acquisition gear and image display gear before and after the fpga algorithm module. This extremely 简化了 veification flow of fpga algorithm.
ps. .mif file is abbreviated from memory initialization file.
原文：http://www.cnblogs.com/sunmaoduo/p/4521159.html