STM32时钟初始化函数SystemInit()详解【转】

 1 static void SetSysClock(void)
 2 {
 3 #ifdef SYSCLK_FREQ_HSE
 4   SetSysClockToHSE();
 5 #elif defined SYSCLK_FREQ_24MHz
 6   SetSysClockTo24();
 7 #elif defined SYSCLK_FREQ_36MHz
 8   SetSysClockTo36();
 9 #elif defined SYSCLK_FREQ_48MHz
10   SetSysClockTo48();
11 #elif defined SYSCLK_FREQ_56MHz
12   SetSysClockTo56();  
13 #elif defined SYSCLK_FREQ_72MHz//我的定义的是SYSCLK_FREQ_72MHz，所以调用SetSysClockTo72()
14   SetSysClockTo72();
15 #endif
16 }

 1 static void SetSysClockTo72(void)
 2 {
 3   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 4    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
 5   /* Enable HSE */    
 6   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 7  
 8   /* Wait till HSE is ready and if Time out is reached exit */
 9   do
10   {
11     HSEStatus = RCC->CR & RCC_CR_HSERDY;
12     StartUpCounter++;  
13   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
14  
15   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
16   {
17     HSEStatus = (uint32_t)0x01;
18   }
19   else
20   {
21     HSEStatus = (uint32_t)0x00;
22   }  
23   if (HSEStatus == (uint32_t)0x01)
24   {
25     /* Enable Prefetch Buffer */
26     FLASH->ACR |= FLASH_ACR_PRFTBE;
27  
28     /* Flash 2 wait state */
29     FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
30     FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
31     /* HCLK = SYSCLK */
32     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
33       
34     /* PCLK2 = HCLK */
35     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
36     
37     /* PCLK1 = HCLK */
38     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
39 #ifdef STM32F10X_CL
40     /* Configure PLLs ------------------------------------------------------*/
41     /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
42     /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
43         
44     RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
45                               RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
46     RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
47                              RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
48      /* Enable PLL2 */
49     RCC->CR |= RCC_CR_PLL2ON;
50     /* Wait till PLL2 is ready */
51     while((RCC->CR & RCC_CR_PLL2RDY) == 0)
52     {
53     }
54       /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
55     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
56     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
57                             RCC_CFGR_PLLMULL9); 
58 #else    
59     /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
60     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
61                                         RCC_CFGR_PLLMULL));
62     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
63 #endif /* STM32F10X_CL */
64  
65     /* Enable PLL */
66     RCC->CR |= RCC_CR_PLLON;
67  
68     /* Wait till PLL is ready */
69     while((RCC->CR & RCC_CR_PLLRDY) == 0)
70     {
71     }
72     
73     /* Select PLL as system clock source */
74     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
75     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
76  
77     /* Wait till PLL is used as system clock source */
78     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
79     {
80     }
81   }
82   else
83   { /* If HSE fails to start-up, the application will have wrong clock 
84          configuration. User can add here some code to deal with this error */
85   }
86 }