跨时钟域信号处理

 1 module cross_clk_domain(
 2 
 3     output  wire  signal1,
 4     output  wire  signal2,
 5 
 6     input    wire  set_signal_condition,
 7     input    wire  clk1,
 8     input    wire  rstn1,
 9 
10     input    wire  clr_signal_condition,
11     input    wire  clk2,
12     input    wire  rstn2
13 );
14 
15 reg  set_signal;
16 reg  set_signal_d;
17 reg  set_signal_dd;
18 reg  clr_signal;
19 reg  clr_signal_d;
20 reg  clr_signal_dd;
21 
22 always @(posedge clk1 or negedge rstn1)begin
23     if(!rstn1)begin
24         set_signal<= 1‘b0;
25     end
26     else if(clr_signal_dd)begin
27         set_signal<= 1‘b0;
28     end
29     else if(set_signal_condition)begin
30         set_signal<= 1‘b1;
31     end
32 end
33 
34 always @(posedge clk2 or negedge rstn2)begin
35     if(!rstn2)begin
36         set_signal_d   <= 1‘b0;
37         set_signal_dd <= 1‘b0;
38     end
39     else begin
40         set_signal_d   <= set_signal;
41         set_signal_dd <= set_signal_d;
42     end
43 end
44 
45 always @(posedge clk2 or negedge rstn2)begin
46     if(!rstn2)begin
47         clr_signal <= 1‘b0;
48     end
49     else if(~set_signal_dd )begin
50         clr_signal <= 1‘b0;
51     end
52     else if(clr_signal_condition)begin
53         clr_signal <= 1‘b1;
54     end
55 end
56 
57 always @(posedge clk1 or negedge rstn1)begin
58     if(!rstn1)begin
59         clr_signal_d   <= 1‘b0;
60         clr_signal_dd <= 1‘b0;
61     end
62     else begin
63         clr_signal_d   <= clr_signal;
64         clr_signal_dd <= clr_signal_d   ;
65     end
66 end
67 
68 assign signal1=set_flag;
69 assign signal2=set_flag_dd;
70 
71 endmodule