FPGA——SCCB协议实现（未完待续）

module SCCB_M(
    clk         ,
    rst_n       ,
    addr        ,
    wr_en       ,
    wdata       ,
    rd_en       ,
    rdata       ,
    rdata_vld   ,
    sclk        ,
    sio_out     ,
    sio_out_en  ,
    sio_din     ,
    rdy         
);
parameter   ADDR_W      =   8;
parameter   DATA_W      =   8;
parameter   DATA_R      =   8;
parameter   IDWADDRESS  =   8‘b01000010;


input                   clk;
input                   rst_n;
input   [ADDR_W-1:0]    addr;
input                   wr_en;
input   [DATA_W-1:0]    wdata;
input                   rd_en;
input                   sio_din;

output  [DATA_R-1:0]    rdata;
output                  rdata_vld;
output                  sclk;
output                  sio_out;
output                  sio_out_en;
output                  rdy;

inout                   sio_d;
//三态门
assign sio_d    = sio_out_en ? sio_out:1‘bz;
assign sio_din  = sio_d;

//sclk 50MHz cycle = 8us
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        cnt_sclk <= 0;
    end
    else if(add_cnt_sclk)begin
        if(end_cnt_sclk)
            cnt_sclk <= 0;
        else
            cnt_sclk <= cnt_sclk + 1‘b1;
    end
end
assign add_cnt_sclk = work_flag;
assign end_cnt_sclk = add_cnt_sclk && cnt_sclk == 400 - 1;

//cnt_byte write
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        cnt_byte <= 0;
    end
    else if(add_cnt_byte)begin
        if(end_cnt_byte)
            cnt_byte <= 0;
        else
            cnt_byte <= cnt_byte + 1‘b1;
    end
end
assign add_cnt_byte = end_cnt_sclk;
assign end_cnt_byte = add_cnt_byte && cnt_byte == 30 - 1;//3*9 +3

//work_flag
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        work_flag <= 0;
    end
    else if(work_flag_1)begin
        work_flag <= 1;
    end
    else if(work_flag_0)begin
        work_flag <= 0;
    end
end
assign work_flag_1 = wr_en;
assign work_flag_0 = end_cnt_byte;

//sclk
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        sclk <= 1;
    end
    else if(sclk_flag_1)begin
        sclk <= 1;
    end
    else if(sclk_flag_0)begin
        sclk <= 0;
    end
end
assign sclk_flag_1 = add_cnt_sclk && cnt_sclk == 200 - 1;
assign sclk_flag_0 = add_cnt_sclk && cnt_sclk == 0 && (!start_flag) && (end_flag);
assign start_flag  = add_cnt_byte && cnt_byte == 0;
assign end_flag    = add_cnt_byte && cnt_byte == 29;//0,1

//write
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        sio_out <= 0;
    end
    else if(sio_out_en)begin
        sio_out <= wdata_tmp[29-cnt_byte];
    end
end
assign sio_out_en = add_cnt_sclk && cnt_sclk == 100 - 1;//时钟宽度 1/4时写入数据

//数据装载
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        subaddr <= 0;
        writedata <= 0;
    end
    else if(data_load)begin
        subaddr <= addr;
        writedata <= wdata;
    end
end
assign data_load = wr_en && !work_flag;

//load data
always @(*)begin
    if(wdata_load)begin
        wdata_tmp = {1‘b0,IDWADDRESS,1‘b1,addr,1‘b1,wdata,1‘b1,2‘b01};
    end
end
assign wdata_load = work_flag;//数据装载完成(work_flag)之后，加载整合数据

endmodule