数据组合---Verilog

 1 module Data_Combination(
 2 
 3     input          wire                  Clk,
 4     input          wire                  Rst_n,
 5 
 6     input          wire                  ShortTrainingEnable,
 7     input          wire    [7:0]         ShortTrainingRe,
 8     input          wire    [7:0]         ShortTrainingIm,
 9 
10     input          wire                  otherFOEDataEnable,
11     input          wire    [7:0]         otherFOEDataRe,
12     input          wire    [7:0]         otherFOEDataIm,
13 
14     output         reg                   FOEDataOutEnable,
15     output         reg     [7:0]         FOEDataOutRe,
16     output         reg     [7:0]         FOEDataOutIm);
17 
18 
19 always@(posedge Clk or negedge Rst_n)
20 begin
21     if (!Rst_n)
22     begin
23         FOEDataOutEnable <= 0;
24         FOEDataOutRe <= 8‘b00000000;
25         FOEDataOutIm <= 8‘b00000000;
26     end
27     else
28     begin
29         if (ShortTrainingEnable)
30         begin
31               /*延时后的短训练序列有效      ******///////
32             FOEDataOutEnable <= 1;
33             FOEDataOutRe <= ShortTrainingRe;
34             FOEDataOutIm <= ShortTrainingIm;
35         end
36         else
37         begin
38               if (otherFOEDataEnable)
39             begin
40                    //长训练和数据序列校正后有效    ******////////             
41                 FOEDataOutEnable <= 1;
42                 FOEDataOutRe <= otherFOEDataRe;
43                 FOEDataOutIm <= otherFOEDataIm;
44             end
45             else
46             begin
47                 FOEDataOutEnable <= 0;
48                 FOEDataOutRe <= 8‘b00000000;
49                 FOEDataOutIm <= 8‘b00000000;
50             end
51         end
52     end
53 end
54 
55 
56 endmodule