状态机的写法，看了这个贴子，保证弄懂状态机，其他帖子就不用看了
状态机三种写法的示例，实现一个序列检测机，检测hello
//一段式有两种写法
//一段式相较两段式，输出会延时一拍，这不知道是错了还是正常的-_-@
module seq_check_hello(
clk,
rst,
x,
led
);
input clk;
input rst;
input [7:0]x;
output reg led;
localparam check_H = 5‘b00001,
check_e = 5‘b00010,
check_l1 = 5‘b00100,
check_l2 = 5‘b01000,
check_o = 5‘b10000;
reg [4:0]state;
always@(posedge clk or negedge rst)
if(!rst)
begin
state <= check_H;
led <= 1‘b0;
end
else
case(state)
check_H : begin
led <= 1‘b0;
if(x == "H")
state <= check_e;
else
state <= check_H;
end
check_e : begin
led <= 1‘b0;
if(x == "e")
state <= check_l1;
else if(x == "H")
state <= check_e;
else
state <= check_H;
end
check_l1: begin
led <= 1‘b0;
if(x == "l")
state <= check_l2;
else if(x == "H")
state <= check_e;
else
state <= check_H;
end
check_l2: begin
led <= 1‘b0;
if(x == "l")
state <= check_o;
else if(x == "H")
state <= check_e;
else
state <= check_H;
end
check_o : begin
if(x == "o")
begin
state <= check_H;
led <= 1‘b1;
end
else if(x == "H")
begin
state <= check_e;
led <= 1‘b0;
end
else
begin
state <= check_H;
led <= 1‘b0;
end
end
default: begin
state <= state;
led <= 1‘b0;
end
endcase
endmodule
//两段式
module seq_check_hello2(
clk,
rst,
x,
led
);
input clk;
input rst;
input [7:0]x;
output reg led;
localparam check_H = 5‘b00001,
check_e = 5‘b00010,
check_l1 = 5‘b00100,
check_l2 = 5‘b01000,
check_o = 5‘b10000;
reg [4:0]state;
always@(posedge clk or negedge rst)
if(!rst)
state <= check_H;
else
case(state)
check_H : begin
if(x == "H")
state <= check_e;
else
state <= check_H;
end
check_e : begin
if(x == "e")
state <= check_l1;
else if(x == "H")
state <= check_e;
else
state <= check_H;
end
check_l1: begin
if(x == "l")
state <= check_l2;
else if(x == "H")
state <= check_e;
else
state <= check_H;
end
check_l2: begin
if(x == "l")
state <= check_o;
else if(x == "H")
state <= check_e;
else
state <= check_H;
end
check_o : begin
if(x == "o")
state <= check_H;
else if(x == "H")
state <= check_e;
else
state <= check_H;
end
default: state <= state;
endcase
//状态机两段式写法，将状态跳转与输出分开来写
//可以看得出来这是一个mealy型的状态机（不仅与当前状态有关，也与当前输入有关）
//这里的第二段采用了时序来写
/*
always@(posedge clk or negedge rst)
if(!rst)
led <= 1‘b0;
else if(state == check_o && x == "o")
led <= 1‘b1;
else
led <= 1‘b0;
*/
//当然也可以使用组合电路来写
always@(*)
if(state == check_o && x == "o")
led = 1‘b1;
else
led = 1‘b0;
endmodule
//三段式
module seq_check_hello3(
clk,
rst,
x,
led
);
input clk;
input rst;
input [7:0]x;
output reg led;
localparam check_H = 5‘b00001,
check_e = 5‘b00010,
check_l1 = 5‘b00100,
check_l2 = 5‘b01000,
check_o = 5‘b10000;
reg [4:0]cstate;//current_state
reg [4:0]nstate;//next_state
//状态机三段式写法，在二段式的基础上，将当前状态与下一状态分开
always@(posedge clk or negedge rst)
if(!rst)
cstate <= check_H;
else
cstate <= nstate;
always@(cstate or x or rst)
begin
if(!rst)
nstate = check_H;
else begin
case(cstate)
check_H :begin
if(x == "H")
nstate = check_e;
else
nstate = check_H;
end
check_e :begin
if(x == "e")
nstate = check_l1;
else if(x == "H")
nstate = check_e;
else
nstate = check_H;
end
check_l1:begin
if(x == "l")
nstate = check_l2;
else if(x == "H")
nstate = check_e;
else
nstate = check_H;
end
check_l2:begin
if(x == "l")
nstate = check_o;
else if(x == "H")
nstate = check_e;
else
nstate = check_H;
end
check_o :begin
if(x == "H")
nstate = check_e;
else
nstate = check_H;
end
default: nstate = nstate;
endcase
end
end
always@(cstate or x or rst)
if(!rst)
led <= 1‘b0;
else if(cstate == check_o && x == "o")
led <= 1‘b1;
else
led <= 1‘b0;
endmodule
一般状态机的状态转移，与输出是可以通过实际需要提炼出来，需要特别注意一种状态机——序列检测机，尤其是数字序列，比如检测10010，不知道大家怎么检测这个序列，我刚开始按照下图写的状态机，发现有问题
后来仔细观察发现有一个序列没有考虑到——10010010，在这个序列中有两个10010，而用上一个状态机只能检测出一个，所以换了下面的状态转移
这样就解决了问题
经仿真后，波形如下图所示
但是此时的输出总是有一拍的延迟，这个问题怎么解决呢如果需要解决的话
还是状态转移图的问题，很明显，上图所示，输出就是会在下一拍输出，但是将状态机拆成两段式，输出是一段，状态跳转是一段，将输出写为组合逻辑，输出就会没有那一拍的延迟
好的状态机标准，好的状态机的标准很多，最重要的几个方面如下：
状态机描述方法，状态机描述时关键是要描述清楚几个状态机的要素，即如何进行状态转移，每个状态的输出是什么，状态转移的条件等。时序电路的状态是一个状态变量集合，这些状态变量在任意时刻的值都包含了为确定电路的未来行为而必需考虑的所有历史信息。一般来说，状态转移部分是同步时序电路而状态的转移条件的判断是组合逻辑。
状态编码原则
二进制（binary）和格雷码（gray-code）适用于触发器资源较少，组合电路资源丰富的情况（CPLD），对于FPGA，适用one-hot code。这样不但充分利用FPGA丰富的触发器资源，还因为只需比较一个bit，速度快，组合电路简单。其中一般规律如下图所示
原因：
FSM输出可以适用task
FSM中的case最好加上default，默认态可以设为初始态
第二段的always(组合部分，赋值用=)里面判断条件一定要包含所有情况！可以用else保证包含完全。
第二段always中**，组合逻辑电平要维持超过一个clock，仿真时注意。****
//识别独热码, a = width‘bxxxxxxx;
genvar i;
generate
for(i=0; i<width; i=i+1)
begin :high
if(i == 0)
assign mask_high[i] = a[i];
else
assign mask_high[i] = a[i] ^ mask_high[i-1];
end
endgenerate
assign is_onehot = (&(mask_high | ~a)) & (|a) ;
assign is_onehot = mask_high[width - 1] & (&(mask_high[width - 2:0] | ~a[width - 2:0]));
assign is_mass = ~&(mask_high | ~a);
原文：https://www.cnblogs.com/HLhello/p/12989573.html