数据扰码器---Verilog代码

module DATA_scramble(

    input    wire         SCRAM_CLK,
    input    wire         SCRAM_RST,
    input    wire  [7:1]  SCRAM_SEED,
    
    input    wire         SCRAM_DIN,
    input    wire         SCRAM_LOAD,
    input    wire         SCRAM_ND,
    
    output   reg          SCRAM_DOUT,
    output   reg          SCRAM_RDY
    );




reg [7:1] SCRAMBLER;

always @ ( negedge SCRAM_RST or posedge SCRAM_CLK )
begin
    if(!SCRAM_RST)
    begin
        SCRAM_DOUT <= 0;
        SCRAM_RDY  <= 0;
        SCRAMBLER  <= 0;
    end
    else 
    begin
        if(SCRAM_LOAD)
            SCRAMBLER <= SCRAM_SEED;
        else 
        begin
            if(SCRAM_ND)
            begin
                SCRAM_DOUT <= SCRAM_DIN + SCRAMBLER [7] + SCRAMBLER [4];                
                SCRAM_RDY  <= 1;                                                    
                SCRAMBLER  <= { SCRAMBLER[6:1], SCRAMBLER [7] + SCRAMBLER [4] };    
            end
            else 
            begin
                SCRAM_DOUT <= 0;    
                SCRAM_RDY  <= 0;
            end
        end
    end
end

endmodule