卷积编码器---Verilog代码

module conv_encoder(

    input      wire             clk,
    input      wire             aclr,
    input      wire             data_in,
    input      wire             nd,
    output     reg   [1:0]      data_out_v,
    output     reg              rdy
    );


reg [6:1] shift_reg;

always @ ( negedge aclr or posedge clk )
begin
    if(!aclr)
    begin
        shift_reg <= 6‘b000000;
        data_out_v <= 0;
        rdy <= 0;
    end
    else 
    begin
        if(nd)
        begin
            data_out_v[0] <= shift_reg[6] + shift_reg[5] + shift_reg[3] + shift_reg[2] + data_in;
            data_out_v[1] <= shift_reg[6] + shift_reg[3] + shift_reg[2] + shift_reg[1] + data_in;
            rdy<=1;
            shift_reg <= { shift_reg [5:1], data_in };
        end
        else 
        begin
            rdy <= 0;
        end
    end
end


endmodule