Verilog Module Parameter可以让例化模块接收参数

//**************************************************************
//            Quantize the signed 12-bit to be signed n-bit Data
//
//
//**************************************************************

module quant_signed_n #(
    parameter WIDTH_OUT = 5 )(
    rst_n,
    ts_sam_clk,
    rdi,
    rdq,
    
    dout_i,
    dout_q
    
    );
    
    //****************************************
    //            Param Def
    //
    //****************************************
    localparam INDEX_BOUND = WIDTH_OUT - 1;
    
    //****************************************
    //            Port Def.
    //
    //****************************************
    input wire rst_n;
    input wire ts_sam_clk;
    
    input wire signed[11:0] rdi;
    input wire signed[11:0] rdq;
    
    output wire signed[INDEX_BOUND:0] dout_i;
    output wire signed[INDEX_BOUND:0] dout_q;
    
    //****************************************
    //            Status Define
    //
    //****************************************
    
    
    //****************************************
    //            Define
    //
    //****************************************

    
    //****************************************
    //            Variables
    //
    //****************************************
    reg signed[INDEX_BOUND:0] di_reg;
    reg signed[INDEX_BOUND:0] dq_reg;
    
    
    //****************************************
    //            Behaviour
    //
    //****************************************
    //***    Driving Output
    assign dout_i = di_reg;
    assign dout_q = dq_reg;
    
    //***    Truncate
    always@(posedge ts_sam_clk)begin
        if(!rst_n)begin
            di_reg <= {WIDTH_OUT{1‘b0}};
            dq_reg <= {WIDTH_OUT{1‘b0}};
        end
        else begin
            di_reg <= rdi[11:11-WIDTH_OUT+1];
            dq_reg <= rdq[11:11-WIDTH_OUT+1];
        end
    end
    
    
endmodule

    wire signed[3:0] rdi_4b;
    wire signed[3:0] rdq_4b;
    //***    Truncation for Short TS to be 5-bit signed
    quant_signed_n #(
    .WIDTH_OUT(4)
    )quant_signed_n_01(
    .rst_n(block_rst_n),
    .ts_sam_clk(ts_sam_clk),
    .rdi(rdi),
    .rdq(rdq),
    .dout_i(rdi_4b),
    .dout_q(rdq_4b)
    );