Verilog中的文件的读取和写入

 1 `timescale 1ns/1ns
 2 
 3 module file_ctrl;
 4 
 5 reg         　　clk;　　　　　　　　　
 6 reg            rst_n;
 7 
 8 reg　　[7:0]　　data_in;                //定义的数据输入寄存器
 9 reg　　[7:0]　　data_out;                        
10 reg　　[7:0]　　cnt;
11 
12 integer　　file_rd;                //定义数据读指针    
13 integer　　file_wr;                //定义数据写指针
14 
15 initial begin                        //定义时钟    
16     clk = 1‘b1;
17     forever
18     #10
19     clk = ~clk;                
20 end    
21 
22 initial begin                        //定义复位
23     rst_n = 1‘b0;
24     #21
25     rst_n = 1‘b1;
26 end
27 
28 initial begin                        //打开读取和写入的文件，这里的路径要对    
29     file_rd = $fopen("E:/Project/file_ctrl/sim/tb/data_in.txt","r");
30     file_wr = $fopen("E:/Project/file_ctrl/sim/tb/data_out.txt","w");
31 end    
32         
33 always@(posedge clk or negedge rst_n)    
34 begin
35     if(rst_n == 1‘b0)begin
36         data_in <= 8‘d0;        
37         cnt <= 8‘d0;
38     end
39     else if(cnt < 10)begin
40         $fscanf(file_rd,"%h",data_in);            //读取每行    
41         cnt <= cnt +1;        
42         $fwrite(file_wr,"%h\n",    data_in);      //换行写入    
43     end
44     else begin
45         data_in <= 8‘d0;
46         $fclose(file_rd);                        //关闭文件
47         $fclose(file_wr);        
48         cnt <= 8‘d11;
49     end
50 end    
51 
52 
53 
54 endmodule