Simple superscalar pipeline.
By fetching and dispatching two instructions at a time,
a maximum of two instructions per cycle can be completed.
(IF = Instruction Fetch, ID = Instruction Decode,
EX = Execute, MEM = Memory access,
WB = Register write back,
i = Instruction number, t = Clock cycle [i.e., time])
power 8
超标量
原文：https://www.cnblogs.com/shaohef/p/12490188.html
