FPGA——异步串行通信(UART)发送

module uart_byte_tx(
clk ,//50MHz时钟
rst_n ,//复位
data_byte ,//数据输入
send_en ,//发送使能(分频计数器)
baud_set ,//波特率设置
rs232_tx ,//数据输出
uart_state ,//串口发送状态
tx_done //单个字节传送完成标志位
);

//参数定义
parameter DATA_W = 8;
parameter BAUS_W = 3;
parameter BAUE_W = 17;
parameter BITC_W = 4;

localparam START_BIT = 1‘b0;//起始位
localparam STOP_BIT = 1‘b1;//停止位

//输入信号定义
input clk ;
input rst_n ;
input [DATA_W-1:0] data_byte ;
input send_en ;
input [BAUS_W-1:0] baud_set ;

//输出信号定义
output rs232_tx ;
output tx_done ;
output uart_state ;

//输出信号reg定义
reg rs232_tx ;
reg uart_state ;
wire tx_done ;

//中间信号定义
reg [BAUE_W-1:0] baud_div ;//波特率分频值
reg [BAUE_W-1:0] cnt_div ;//分频计数器
reg [BITC_W-1:0] bit_cnt ;//比特位计数器

//时序逻辑写法
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
baud_div <= 0;
end
else begin
case (baud_set)
0 : baud_div <= 17‘d83333;//600bps
1 : baud_div <= 17‘d41666;//1200bps
2 : baud_div <= 17‘d20833;//2400bps
3 : baud_div <= 17‘d10416;//4800bps
4 : baud_div <= 17‘d5208 ;//9600bps
5 : baud_div <= 17‘d2604 ;//19200bps
6 : baud_div <= 17‘d1302 ;//38400bps
7 : baud_div <= 17‘d868 ;//57600bps
default:
baud_div <= 0;
endcase
end
end

always@(posedge clk or negedge rst_n)begin
if(rst_n==1‘b0)begin
uart_state <= 0;
end
else if(send_en) begin
uart_state <= 1;
end
else if(end_bit_cnt)begin
//数据传送时，send_en关闭,数据在传送完该字节后，结束传送
uart_state <= 0;
end
end

wire add_cnt_div;
wire end_cnt_div;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt_div <= 0;
end
else if(add_cnt_div)begin
if(end_cnt_div)
cnt_div <= 0;
else
cnt_div <= cnt_div + 1‘b1;
end
end
assign add_cnt_div = (uart_state == 1);
assign end_cnt_div = add_cnt_div && cnt_div == baud_div - 1 ;

wire add_bit_cnt;
wire end_bit_cnt;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
bit_cnt <= 0;
end
else if(add_bit_cnt)begin
if(end_bit_cnt)
bit_cnt <= 0;
else
bit_cnt <= bit_cnt + 1‘b1;
end
end
assign add_bit_cnt = (end_cnt_div == 1);
assign end_bit_cnt = add_bit_cnt && bit_cnt == 10 - 1 ;

always@(posedge clk or negedge rst_n)begin
if(rst_n==1‘b0)begin
rs232_tx <= 1‘b1;//空闲位
end
else begin
case (bit_cnt)
4‘d0 : rs232_tx <= START_BIT ;
4‘d1 : rs232_tx <= data_byte[0];
4‘d2 : rs232_tx <= data_byte[1];
4‘d3 : rs232_tx <= data_byte[2];
4‘d4 : rs232_tx <= data_byte[3];
4‘d5 : rs232_tx <= data_byte[4];
4‘d6 : rs232_tx <= data_byte[5];
4‘d7 : rs232_tx <= data_byte[6];
4‘d8 : rs232_tx <= data_byte[7];
4‘d9 : rs232_tx <= STOP_BIT ;
default: rs232_tx <= 1‘b1;
endcase
end
end

assign tx_done = (end_bit_cnt == 1);

endmodule