idelay3 cascade

module idelay_cascade(
data_in,data_out,
RST,REFCLK,
RDY
    );
input   data_in;
output  data_out;

input   RST,REFCLK;
output  RDY;


IDELAYE3 #(
    .CASCADE("MASTER"), // Cascade setting (NONE, MASTER, SLAVE_END, SLAVE_MIDDLE)
    .DELAY_FORMAT("TIME"), // Units of the DELAY_VALUE (TIME, COUNT)
    .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
    .DELAY_TYPE("FIXED"), // Set the type of tap delay line (FIXED, VAR_LOAD, VARIABLE)
    .DELAY_VALUE(50), // Input delay value setting
    .IS_CLK_INVERTED(1'b0), // Optional inversion for CLK
    .IS_RST_INVERTED(1'b0), // Optional inversion for RST
    .REFCLK_FREQUENCY(300.0), // IDELAYCTRL clock input frequency in MHz (VALUES)
    .UPDATE_MODE("ASYNC") // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
    )
IDELAYE3_in (
    .CASC_OUT(CASC_OUT_a), // 1-bit output: Cascade delay output to ODELAY input cascade
    .CNTVALUEOUT(), // 9-bit output: Counter value output
    .DATAOUT(data_out), // 1-bit output: Delayed data output
    .CASC_IN(), // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT
    .CASC_RETURN(CASC_OUT_d), // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT
    .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
    .CLK(), // 1-bit input: Clock input
    .CNTVALUEIN(), // 9-bit input: Counter value input
    .DATAIN(), // 1-bit input: Data input from the IOBUF
    .EN_VTC(1'b1), // 1-bit input: Keep delay constant over VT
    .IDATAIN(data_in), // 1-bit input: Data input from the logic
    .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
    .LOAD(1'b0), // 1-bit input: Load DELAY_VALUE input
    .RST(RST) // 1-bit input: Asynchronous Reset to the DELAY_VALUE
    );



// Xilinx HDL Libraries Guide, version 2014.1
ODELAYE3 #(
.CASCADE("SLAVE_MIDDLE"), // Cascade setting (NONE, MASTER, SLAVE_END, SLAVE_MIDDLE)
.DELAY_FORMAT("TIME"), // (TIME, COUNT)
.DELAY_TYPE("FIXED"), // Set the type of tap delay line (FIXED, VAR_LOAD, VARIABLE)
.DELAY_VALUE(50), // Output delay tap setting
.IS_CLK_INVERTED(1'b0), // Optional inversion for CLK
.IS_RST_INVERTED(1'b0), // Optional inversion for RST
.REFCLK_FREQUENCY(300.0), // IDELAYCTRL clock input frequency in MHz (VALUES).
.UPDATE_MODE("ASYNC") // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
)
ODELAYE3_inst (
.CASC_OUT(CASC_OUT_b), // 1-bit output: Cascade delay output to IDELAY input cascade
.CNTVALUEOUT(), // 9-bit output: Counter value output
.DATAOUT(CASC_OUT_d), // 1-bit output: Delayed data from ODATAIN input port
.CASC_IN(CASC_OUT_a), // 1-bit input: Cascade delay input from slave IDELAY CASCADE_OUT
.CASC_RETURN(CASC_OUT_c), // 1-bit input: Cascade delay returning from slave IDELAY DATAOUT
.CE(1'b0), // 1-bit input: Active high enable increment/decrement input
.CLK(), // 1-bit input: Clock input
.CNTVALUEIN(), // 9-bit input: Counter value input
.EN_VTC(1'b1), // 1-bit input: Keep delay constant over VT
.INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
.LOAD(1'b0), // 1-bit input: Load DELAY_VALUE input
.ODATAIN(), // 1-bit input: Data input
.RST(RST) // 1-bit input: Asynchronous Reset to the DELAY_VALUE
);




IDELAYE3 #(
    .CASCADE("SLAVE_END"), // Cascade setting (NONE, MASTER, SLAVE_END, SLAVE_MIDDLE)
    .DELAY_FORMAT("TIME"), // Units of the DELAY_VALUE (TIME, COUNT)
    .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
    .DELAY_TYPE("FIXED"), // Set the type of tap delay line (FIXED, VAR_LOAD, VARIABLE)
    .DELAY_VALUE(50), // Input delay value setting
    .IS_CLK_INVERTED(1'b0), // Optional inversion for CLK
    .IS_RST_INVERTED(1'b0), // Optional inversion for RST
    .REFCLK_FREQUENCY(300.0), // IDELAYCTRL clock input frequency in MHz (VALUES)
    .UPDATE_MODE("ASYNC") // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
    )
IDELAYE3_out (
    .CASC_OUT(), // 1-bit output: Cascade delay output to ODELAY input cascade
    .CNTVALUEOUT(), // 9-bit output: Counter value output
    .DATAOUT(CASC_OUT_c), // 1-bit output: Delayed data output
    .CASC_IN(CASC_OUT_b), // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT
    .CASC_RETURN(), // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT
    .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
    .CLK(), // 1-bit input: Clock input
    .CNTVALUEIN(), // 9-bit input: Counter value input
    .DATAIN(), // 1-bit input: Data input from the IOBUF
    .EN_VTC(1'b1), // 1-bit input: Keep delay constant over VT
    .IDATAIN(), // 1-bit input: Data input from the logic
    .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
    .LOAD(1'b0), // 1-bit input: Load DELAY_VALUE input
    .RST(RST) // 1-bit input: Asynchronous Reset to the DELAY_VALUE
    );


IDELAYCTRL #(.SIM_DEVICE("ULTRASCALE"))

IDELAYCTRL_inst (
.RDY(RDY), // 1-bit output: Ready output
.REFCLK(REFCLK), // 1-bit input: Reference clock input
.RST(RST) // 1-bit input: Active high reset input
);


endmodule

idelay3 cascade

原文：https://www.cnblogs.com/liqi120150/p/11047086.html