1080P60视频源---verilog
1 `timescale 1ns / 1ps 2 ////////////////////////////////////////////////////////////////////////////////// 3 // Company: 4 // Engineer: chensimin 5 // 6 // Create Date: 2019/03/15 10:09:21 7 // Design Name: 8 // Module Name: video_source 9 // Project Name: 10 // Target Devices: 11 // Tool Versions: 12 // Description: 13 // 14 // Dependencies: 15 // 16 // Revision: 17 // Revision 0.01 - File Created 18 // Additional Comments: 19 // 20 ////////////////////////////////////////////////////////////////////////////////// 21 22 module video_source ( 23 24 input wire clk, 25 input wire rest, 26 output reg [9:0] video_y = 10‘h3FF, 27 output reg [9:0] video_c = 10‘h3FF, 28 output wire data_enable, 29 output reg sync_h = 0, 30 output reg sync_v = 0 31 32 ); 33 34 //--------------------------------------------------------------------------------------------------------------- 35 36 reg [11:0] h_count = 2199; 37 38 always @(posedge clk or posedge rest) 39 begin 40 if(rest) 41 h_count <= 12‘d2199; 42 else if(h_count == 12‘d2199) 43 h_count <= 12‘d0; 44 else 45 h_count <= h_count + 1‘d1; 46 end 47 48 //--------------------------------------------------------------------------------------------------------------- 49 50 reg h_end = 0; 51 52 always @(posedge clk or posedge rest) 53 begin 54 if(rest) 55 h_end <= 1‘b0; 56 else if(h_count == 12‘d2198) 57 h_end <= 1‘b1; 58 else 59 h_end <= 1‘b0; 60 end 61 62 //--------------------------------------------------------------------------------------------------------------- 63 64 reg [11:0] v_count = 1; 65 66 always @(posedge clk or posedge rest) 67 begin 68 if(rest) 69 v_count <= 12‘d1; 70 else if(v_count == 12‘d1125 & h_count == 12‘d2199) 71 v_count <= 12‘d1; 72 else if(h_end) 73 v_count <= v_count + 1‘d1; 74 end 75 76 //--------------------------------------------------------------------------------------------------------------- 77 78 wire b0, b1, b2, b3, b4, b5, b6, b7; 79 wire [7:0] condition_b; 80 81 assign b0 = v_count >= 12‘d1 & v_count < 12‘d41 ; 82 assign b1 = v_count == 12‘d41 & h_count <= 12‘d2198 ; 83 assign b2 = v_count >= 12‘d42 & v_count < 12‘d1121 ; 84 assign b3 = v_count == 12‘d1121 & h_count <= 12‘d2198 ; 85 assign b4 = v_count == 12‘d1121 & h_count == 12‘d2199 ; 86 assign b5 = v_count >= 12‘d1122 & v_count < 12‘d1125 ; 87 assign b6 = v_count == 12‘d1125 & h_count <= 12‘d2198 ; 88 assign b7 = v_count == 12‘d1125 & h_count == 12‘d2199 ; 89 90 assign condition_b = {b0, b1, b2, b3, b4, b5, b6, b7}; 91 92 //--------------------------------------------------------------------------------------------------------------- 93 94 reg v = 0; 95 96 always @(posedge clk or posedge rest) 97 begin 98 if(rest) 99 v <= 1‘b0; 100 else 101 begin 102 case(condition_b) 103 8‘b1000_0000: 104 v <= 1‘b1; 105 8‘b0100_0000: 106 v <= 1‘b1; 107 8‘b0010_0000: 108 v <= 1‘b0; 109 8‘b0001_0000: 110 v <= 1‘b0; 111 8‘b0000_1000: 112 v <= 1‘b1; 113 8‘b0000_0100: 114 v <= 1‘b1; 115 8‘b0000_0010: 116 v <= 1‘b1; 117 8‘b0000_0001: 118 v <= 1‘b1; 119 default: 120 v <= 1‘b0; 121 endcase 122 end 123 end 124 125 //--------------------------------------------------------------------------------------------------------------- 126 127 wire [9:0] condition_a ; 128 129 assign a0 = h_count == 12‘d2199 ; // 3FF 130 assign a1 = h_count == 12‘d0 ; // 000 131 assign a2 = h_count == 12‘d1 ; // 000 132 assign a3 = h_count == 12‘d2 ; // EAV 133 assign a4 = h_count >= 12‘d3 & h_count <= 274 ; // Blank 134 assign a5 = h_count == 12‘d275 ; // 3FF 135 assign a6 = h_count == 12‘d276 ; // 000 136 assign a7 = h_count == 12‘d277 ; // 000 137 assign a8 = h_count == 12‘d278 ; // SAV 138 assign a9 = h_count >= 12‘d279 & h_count <= 2198 ; // Active 139 140 141 assign condition_a = {a0, a1, a2, a3, a4, a5, a6, a7, a8, a9}; 142 143 //--------------------------------------------------------------------------------------------------------------- 144 145 reg eav = 0; 146 reg sav = 0; 147 148 always @(posedge clk or posedge rest) 149 begin 150 if(rest) 151 begin 152 video_y <= 10‘h3FF; 153 eav <= 1‘b0; 154 sav <= 1‘b0; 155 end 156 else 157 begin 158 159 eav <= 1‘b0; 160 sav <= 1‘b0; 161 162 case(condition_a) 163 10‘b100_0000_000: 164 video_y <= 10‘h3FF; 165 10‘b010_0000_000: 166 video_y <= 10‘h000; 167 10‘b001_0000_000: 168 video_y <= 10‘h000; 169 10‘b000_1000_000: 170 begin 171 eav <= 1‘b1; 172 if( v_count >=42 & v_count <= 1121) 173 video_y <= {1‘b1, 1‘b0, 1‘b0, 1‘b1, 1‘b0^1‘b1, 1‘b0^1‘b1, 1‘b0^1‘b0, 1‘b0^1‘b0^1‘b1, 1‘b0, 1‘b0}; 174 else 175 video_y <= {1‘b1, 1‘b0, 1‘b1, 1‘b1, 1‘b1^1‘b1, 1‘b0^1‘b1, 1‘b0^1‘b1, 1‘b0^1‘b1^1‘b1, 1‘b0, 1‘b0}; 176 end 177 10‘b000_0100_000: 178 video_y <= 10‘h040; 179 10‘b000_0010_000: 180 video_y <= 10‘h3FF; 181 10‘b000_0001_000: 182 video_y <= 10‘h000; 183 10‘b000_0000_100: 184 video_y <= 10‘h000; 185 10‘b000_0000_010: 186 begin 187 sav <= 1‘b1; 188 if( v_count >= 42 & v_count <= 1121) 189 video_y <= {1‘b1, 1‘b0, 1‘b0, 1‘b0, 1‘b0^1‘b0, 1‘b0^1‘b0, 1‘b0^1‘b0, 1‘b0^1‘b0^1‘b0, 1‘b0, 1‘b0}; 190 else 191 video_y <= {1‘b1, 1‘b0, 1‘b1, 1‘b0, 1‘b1^1‘b0, 1‘b0^1‘b0, 1‘b0^1‘b1, 1‘b0^1‘b1^1‘b0, 1‘b0, 1‘b0}; 192 end 193 10‘b000_0000_001: 194 video_y <= 10‘h0CD; 195 default: 196 video_y <= 10‘h040; 197 endcase 198 end 199 end 200 201 //--------------------------------------------------------------------------------------------------------------- 202 203 always @(posedge clk or posedge rest) 204 begin 205 if(rest) 206 video_c <= 10‘h3FF; 207 else 208 begin 209 210 case(condition_a) 211 10‘b100_0000_000: 212 video_c <= 10‘h3FF; 213 10‘b010_0000_000: 214 video_c <= 10‘h000; 215 10‘b001_0000_000: 216 video_c <= 10‘h000; 217 10‘b000_1000_000: 218 begin 219 if( v_count >=42 & v_count <= 1121) 220 video_c <= {1‘b1, 1‘b0, 1‘b0, 1‘b1, 1‘b0^1‘b1, 1‘b0^1‘b1, 1‘b0^1‘b0, 1‘b0^1‘b0^1‘b1, 1‘b0, 1‘b0}; 221 else 222 video_c <= {1‘b1, 1‘b0, 1‘b1, 1‘b1, 1‘b1^1‘b1, 1‘b0^1‘b1, 1‘b0^1‘b1, 1‘b0^1‘b1^1‘b1, 1‘b0, 1‘b0}; 223 end 224 10‘b000_0100_000: 225 video_c <= 10‘h040; 226 10‘b000_0010_000: 227 video_c <= 10‘h3FF; 228 10‘b000_0001_000: 229 video_c <= 10‘h000; 230 10‘b000_0000_100: 231 video_c <= 10‘h000; 232 10‘b000_0000_010: 233 begin 234 if( v_count >= 42 & v_count <= 1121) 235 video_c <= {1‘b1, 1‘b0, 1‘b0, 1‘b0, 1‘b0^1‘b0, 1‘b0^1‘b0, 1‘b0^1‘b0, 1‘b0^1‘b0^1‘b0, 1‘b0, 1‘b0}; 236 else 237 video_c <= {1‘b1, 1‘b0, 1‘b1, 1‘b0, 1‘b1^1‘b0, 1‘b0^1‘b0, 1‘b0^1‘b1, 1‘b0^1‘b1^1‘b0, 1‘b0, 1‘b0}; 238 end 239 10‘b000_0000_001: 240 video_c <= 10‘h0CD; 241 default: 242 video_c <= 10‘h040; 243 endcase 244 end 245 end 246 247 //--------------------------------------------------------------------------------------------------------------- 248 249 reg h = 0; 250 251 always @(posedge clk or posedge rest) 252 begin 253 if(rest) 254 h <= 1‘b0; 255 else if(h_count == 2199 | ( h_count >= 0 & h_count <= 278 )) 256 h <= 1‘b0; 257 else 258 h <= 1‘b1; 259 end 260 261 //--------------------------------------------------------------------------------------------------------------- 262 263 assign data_enable = h & ~v; 264 265 //--------------------------------------------------------------------------------------------------------------- 266 267 always @(posedge clk or posedge rest) 268 begin 269 if(rest) 270 sync_h <= 1‘b0; 271 else if(h_count >= 87 & h_count <= 130) 272 sync_h <= 1‘b1; 273 else 274 sync_h <= 1‘b0; 275 end 276 277 //--------------------------------------------------------------------------------------------------------------- 278 279 always @(posedge clk or posedge rest) 280 begin 281 if(rest) 282 sync_v <= 1‘b0; 283 else if(v_count >=1 & v_count < 5) 284 sync_v <= 1‘b1; 285 else if(v_count == 5 & h_count <=2198) 286 sync_v <= 1‘b1; 287 else 288 sync_v <= 1‘b0; 289 end 290 291 //--------------------------------------------------------------------------------------------------------------- 292 293 endmodule 294 295 296 /* 297 298 add_force {/video_source/clk} -radix hex {1 0ns} {0 50000ps} -repeat_every 100000ps 299 add_force {/video_source/rest} -radix hex {1 0ns} {0 200ns} 300 301 302 303 304 */
仿真结果：
原文：https://www.cnblogs.com/chensimin1990/p/10559021.html