这篇文章主要介绍一下verilog读ov7670的出厂序列号
读时序共分为五个部分
ov7670管脚
简单的列一下程序
IIC时钟对时钟要求不严格,所以采用进位的方法进行分频,所产生的时钟频率略小于100K,
div_en是使能信号,如果采用使能时钟可能会出现问题。
//-------------------------------- //Funtion : sda_reg always @(posedge clk or negedge rst_n) begin if(!rst_n) begin iic_clk1 <= 1‘d1; sda_reg <= 1‘d1; riic_data <= 1‘d0; end else if(dir == 1‘b1) //read case(time_cnt) //idle 6‘d0 : begin iic_clk1 <= 1‘d1; sda_reg <= 1‘d1; end //start 6‘d1 :begin iic_clk1 <= 1‘d1; sda_reg <= 1‘d0; end 6‘d2 :begin iic_clk1 <= 1‘d0; sda_reg <= 1‘d0; end //ID_addr 6‘d3 : sda_reg <= wdata_reg[23]; 6‘d4 : sda_reg <= wdata_reg[22]; 6‘d5 : sda_reg <= wdata_reg[21]; 6‘d6 : sda_reg <= wdata_reg[20]; 6‘d7 : sda_reg <= wdata_reg[19]; 6‘d8 : sda_reg <= wdata_reg[18]; 6‘d9 : sda_reg <= wdata_reg[17]; 6‘d10: sda_reg <= wdata_reg[16]; //ack 6‘d11: iic_clk1<= 1‘d0; 6‘d12: ; 6‘d13: iic_clk1<= 1‘d0; //sub_addr 6‘d14: sda_reg <= wdata_reg[15]; 6‘d15: sda_reg <= wdata_reg[14]; 6‘d16: sda_reg <= wdata_reg[13]; 6‘d17: sda_reg <= wdata_reg[12]; 6‘d18: sda_reg <= wdata_reg[11]; 6‘d19: sda_reg <= wdata_reg[10]; 6‘d20: sda_reg <= wdata_reg[9]; 6‘d21: sda_reg <= wdata_reg[8]; //ack 6‘d22: iic_clk1<= 1‘d0; 6‘d23: ; 6‘d24: iic_clk1<= 1‘d0; //stop 6‘d25:begin iic_clk1 <= 1‘d1; sda_reg <= 1‘d0; end 6‘d26:begin iic_clk1 <= 1‘d1; sda_reg <= 1‘d1; end //start 6‘d27:begin iic_clk1 <= 1‘d1; sda_reg <= 1‘d1; end 6‘d28:begin iic_clk1 <= 1‘d1; sda_reg <= 1‘d0; end //ID_addr 6‘d29: sda_reg <= wdata_reg[7]; 6‘d30: sda_reg <= wdata_reg[6]; 6‘d31: sda_reg <= wdata_reg[5]; 6‘d32: sda_reg <= wdata_reg[4]; 6‘d33: sda_reg <= wdata_reg[3]; 6‘d34: sda_reg <= wdata_reg[2]; 6‘d35: sda_reg <= wdata_reg[1]; 6‘d36: sda_reg <= wdata_reg[0]; //ack 6‘d37: iic_clk1<= 1‘d0; 6‘d38: ; 6‘d39: iic_clk1<= 1‘d0; //read_data 6‘d40: riic_data[7] <= iic_sda; 6‘d41: riic_data[6] <= iic_sda; 6‘d42: riic_data[5] <= iic_sda; 6‘d43: riic_data[4] <= iic_sda; 6‘d44: riic_data[3] <= iic_sda; 6‘d45: riic_data[2] <= iic_sda; 6‘d46: riic_data[1] <= iic_sda; 6‘d47: riic_data[0] <= iic_sda; //nack 6‘d48: sda_reg <= 1‘d1; //stop 6‘d49:begin iic_clk1 <= 1‘d1; sda_reg <= 1‘d0; end 6‘d50:begin iic_clk1 <= 1‘d1; sda_reg <= 1‘d1; end default : begin iic_clk1 <= 1‘d1; sda_reg <= 1‘d1; end endcase end
sda是双向端口,在输入的1时候设置为高阻态
dir是读写方向控制段,这里只是读所以置一
原文:http://www.cnblogs.com/bixiaopengblog/p/7527942.html