systemverilog - 数据类型

 1 /*----------------------------------------------------------------------------------
 2 -- Company: 
 3 -- Engineer: 
 4 -- 
 5 -- Create Date: 2011/03/08 21:41:14
 6 -- Design Name: 
 7 -- Module Name:      
 8 -- Project Name: 
 9 -- Target Devices: 
10 -- Tool Versions: 
11 -- Description: 
12 -- 
13 -- Dependencies:  
14 --                                        
15 --                                                                                           
16 --
17 -- Revision:
18 -- Revision 0.01 - File Created
19 -- Additional Comments:
20 --                                                  
21 ----------------------------------------------------------------------------------*/
22 
23 `timescale 1ns / 1ps
24 
25 module hello_world();
26 
27 import uvm_pkg::*;   
28 
29 `include "uvm_macros.svh" 
30  
31 localparam            CYCLE    =    5‘d20    ;
32  
33 logic        clock    ;
34 logic        reset    ;
35  
36 initial begin   
37     `uvm_info ("info1","Hello World!", UVM_LOW)   
38     `uvm_info ("info2","Hello World!", UVM_LOW)  
39     `uvm_info ("info3","Hello World!", UVM_LOW)  
40     `uvm_info ("info4","Hello World!", UVM_LOW)  
41 end
42 
43 initial begin
44     clock = 0 ;
45     forever # (CYCLE/2) clock = !clock ;
46 end 
47 
48 initial begin
49     reset = 1 ;
50     #40
51     reset = 0 ;
52 end 
53  
54  
55 //dut   u1
56 //(
57 ///*input                     */.clk            (               ),
58 ///*input                     */.rst_n        (               ),
59 ///*input        [7:0]     */.rxd            (               ),
60 ///*input                     */.rx_dv        (               ),
61 ///*output     [7:0]     */.txd            (               ),
62 ///*output                     */.tx_en        (               )
63 //);
64   
65  
66 endmodule