[TMS320C674x] 二、GPIO中断

  /* 全局变量 */
  unsigned char Flag=0;

int main(void)
{
    // 外设使能配置
    PSCInit()    
    // GPIO 管脚复用配置
    GPIOBankPinMuxSet();
    // GPIO 管脚初始化
    GPIOBankPinInit();
    // DSP 中断初始化
    InterruptInit();
    // GPIO 管脚中断初始化
    GPIOBankPinInterruptInit();

    unsigned int i;
    // 主循环
    for(;;)
    {
        // 亦可以使用查询法查询中断状态
        if(Flag)
        {
            // 核心板 LED
            for(i=0x00FFFFFF;i>0;i--);                          // 延时
            GPIOPinWrite(SOC_GPIO_0_REGS, 109, GPIO_PIN_LOW);
            GPIOPinWrite(SOC_GPIO_0_REGS, 110, GPIO_PIN_HIGH);

            for(i=0x00FFFFFF;i>0;i--);                          // 延时
            GPIOPinWrite(SOC_GPIO_0_REGS, 109, GPIO_PIN_HIGH);
            GPIOPinWrite(SOC_GPIO_0_REGS, 110, GPIO_PIN_LOW);
        }
    }
}

void InterruptInit(void)
{
    // 初始化 DSP 中断控制器
    IntDSPINTCInit();

    // 使能 DSP 全局中断
    IntGlobalEnable();
}

void GPIOBankPinInterruptInit(void)
{
    // 底板按键中断
    // 配置 USER0 KEY GPIO0[6] 为下降沿触发
    GPIOIntTypeSet(SOC_GPIO_0_REGS, 7, GPIO_INT_TYPE_FALLEDGE);
    // 配置 USER1 KEY GPIO6[1] 为上升沿及下降沿触发
    GPIOIntTypeSet(SOC_GPIO_0_REGS, 98, GPIO_INT_TYPE_BOTHEDGE);

    // 使能 GPIO BANK 中断
    GPIOBankIntEnable(SOC_GPIO_0_REGS, 0);                  // USER0 KEY GPIO0
    GPIOBankIntEnable(SOC_GPIO_0_REGS, 6);                  // USER1 KEY GPIO6

    // 注册中断服务函数
    IntRegister(C674X_MASK_INT4, USER0KEYIsr);              //USER0KEYIsr 是中断服务程序
    IntRegister(C674X_MASK_INT5, USER1KEYIsr);

    // 映射中断到 DSP 可屏蔽中断
    IntEventMap(C674X_MASK_INT4, SYS_INT_GPIO_B0INT);
    IntEventMap(C674X_MASK_INT5, SYS_INT_GPIO_B6INT);

    // 使能 DSP 可屏蔽中断
    IntEnable(C674X_MASK_INT4);
    IntEnable(C674X_MASK_INT5);
}

 * \brief   This function configures the trigger level type for which an 
 *          interrupt is required to occur.
 * 
 * \param   baseAdd    The memory address of the GPIO instance being used.
 *
 * \param   pinNumber  The serial number of the GPIO pin.
 *                     The 144 GPIO pins have serial numbers from 1 to 144. 
 *
 * \param   intType    This specifies the trigger level type. This can take 
 *                     one of the following four values:
 *                     1> GPIO_INT_TYPE_NOEDGE, to not generate any interrupts.
 *                     2> GPIO_INT_TYPE_FALLEDGE, to generate an interrupt on 
 *                        the falling edge of a signal on that pin. 
 *                     3> GPIO_INT_TYPE_RISEDGE, to generate an interrupt on the 
 *                        rising edge of a signal on that pin.
 *                     4> GPIO_INT_TYPE_BOTHEDGE, to generate interrupts on both
 *                        rising and falling edges of a signal on that pin.
 *
 * \return   None.
 *
 * \note     Configuring the trigger level type for generating interrupts is not 
 *           enough for the GPIO module to generate interrupts. The user should 
 *           also enable the interrupt generation capability for the bank to which
 *           the pin belongs to. Use the function GPIOBankIntEnable() to do the same.             

void GPIOIntTypeSet(unsigned int baseAdd, unsigned int pinNumber, 
                    unsigned int intType)
{
    unsigned int regNumber = 0;
    unsigned int pinOffset = 0;
    /*
    ** Each register contains settings for each pin of two banks. The 32 bits
    ** represent 16 pins each from the banks. Thus the register number must be
    ** calculated based on 32 pins boundary.
    */
    regNumber = (pinNumber - 1)/32;
    /*
    ** In every register the least significant bits starts with a GPIO number on
    ** a boundary of 32. Thus the pin offset must be calculated based on 32
    ** pins boundary. Ex: ‘pinNumber‘ of 1 corresponds to bit 0 in
    ** ‘register_name01‘.
    */    
    pinOffset = (pinNumber - 1) % 32;

    switch (intType)
    {
        case GPIO_INT_TYPE_RISEDGE:
            /* Setting Rising edge and clearing Falling edge trigger levels.*/
            HWREG(baseAdd + GPIO_SET_RIS_TRIG(regNumber)) = (1 << pinOffset);
            HWREG(baseAdd + GPIO_CLR_FAL_TRIG(regNumber)) = (1 << pinOffset);
            break;

        case GPIO_INT_TYPE_FALLEDGE:
            /* Setting Falling edge and clearing Rising edge trigger levels.*/ 
            HWREG(baseAdd + GPIO_SET_FAL_TRIG(regNumber)) = (1 << pinOffset);
            HWREG(baseAdd + GPIO_CLR_RIS_TRIG(regNumber)) = (1 << pinOffset);
            break;

        case GPIO_INT_TYPE_BOTHEDGE:
            /* Setting both Rising and Falling edge trigger levels.*/
            HWREG(baseAdd + GPIO_SET_RIS_TRIG(regNumber)) = (1 << pinOffset);
            HWREG(baseAdd + GPIO_SET_FAL_TRIG(regNumber)) = (1 << pinOffset);
            break;

        case GPIO_INT_TYPE_NOEDGE:
            /* Clearing both Rising and Falling edge trigger levels. */
            HWREG(baseAdd + GPIO_CLR_RIS_TRIG(regNumber)) = (1 << pinOffset);
            HWREG(baseAdd + GPIO_CLR_FAL_TRIG(regNumber)) = (1 << pinOffset);
            break;
        default:
            break;
    }
}

 * \brief   This function enables the interrupt generation capability for the
 *          bank of GPIO pins specified.
 *
 * \param   baseAdd     The memory address of the GPIO instance being used.
 * \param   bankNumber  This is the bank for whose pins interrupt generation 
 *                      capabiility needs to be enabled.
 *                      bankNumber is 0 for bank 0, 1 for bank 1 and so on.
 * \return  None. 

void GPIOBankIntEnable(unsigned int baseAdd, unsigned int bankNumber)
{
    HWREG(baseAdd + GPIO_BINTEN) |= (1 << bankNumber);
} 

 * \function IntRegister
 *
 * \brief    Registers an interrupt service routine in the interrupt
 *           vector table for CPU maskable interrupts, NMI, or 
 *           reserved interrupts.
 *
 * \param    cpuINT - CPU maskable interrupt number (4-15), NMI (1),
 *           or reserved interrupt (2-3)
 * \param    userISR - Function pointer to the ISR
 *
 * \return   None
 */
void IntRegister (unsigned int cpuINT, void (*userISR)(void))
{
    /* Check the CPU maskable interrupt number */
    ASSERT(((cpuINT >= 1) && (cpuINT <= 15)));
    
    /* Assign the user‘s ISR to the CPU maskable interrupt */
    c674xISRtbl[cpuINT] = userISR;
}

 * \function IntEventMap
 *
 * \brief    This API maps a system event to a CPU maskable interrupt.
 *
 * \param    cpuINT - CPU maskable interrupt number
 * \param    sysINT - System event number
 *
 * \return   None
 */
void IntEventMap (unsigned int cpuINT, unsigned int sysINT)
{
    unsigned int dspintcREG, restoreVal;

    /* Check the CPU maskable interrupt number */
    ASSERT(((cpuINT >= 4) && (cpuINT <= 15)));
    
    /* Check the system event number */
    ASSERT((sysINT <= 127));
    
    /* Get the address of the correct interrupt mux register */
    dspintcREG = SOC_INTC_0_REGS + DSPINTC_INTMUX((cpuINT >> 2));

    /* Disable interrupts */
    restoreVal = IntGlobalDisable();

    /* Clear and set INTSELx with system event number */
    HWREG(dspintcREG) = (HWREG(dspintcREG) &
            ~DSPINTC_INTMUX_INTSEL(cpuINT)) |
            (sysINT << DSPINTC_INTMUX_INTSEL_SHIFT(cpuINT));

    /* Clear any residual interrupt */
    ICR = (1 << cpuINT);

    /* Restore interrupts */
    IntGlobalRestore(restoreVal);
}

/**
 * \function IntEnable
 *
 * \brief    This API enables a CPU maskable interrupt.
 *
 * \param    cpuINT - CPU maskable interrupt number
 *
 * \return   None
 */
void IntEnable (unsigned int cpuINT)
{
    unsigned int restoreVal;

    /* Check the CPU maskable interrupt number */
    ASSERT(((cpuINT >= 4) && (cpuINT <= 15)));
    
    /* Disable interrupts */
    restoreVal = IntGlobalDisable();

    /* Enable CPU maskable interrupt */
    IER |= (1 << cpuINT);

    /* Restore interrupts */
    IntGlobalRestore(restoreVal);
}