在ISE的例程中看到了下列对Mealy Moore状态机的表述。
the general recommendation for the
-- choice of state-machine depends on the target architecture and specifics of
-- the state-machine size and behavior however typically, Moore style
-- state-machines implement better for FPGAs and Mealy implement best for
-- CPLDs.
-- Mealy vs. Moore Styles
--
-- There are two well known implementation styles for state-machines, Mealy
-- and Moore. The main difference between Mealy and Moore styles is the Mealy
-- state-machine determines the output values based on both the current state
-- state as well as the inputs to the state-machine where Moore determines its
-- outputs solely on the state. In general, Moore type of state-machines
-- implement best in FPGAs due to the fact that most often one-hot
-- state-machines are the chosen encoding method and there is little or no
-- decode and thus logic necessary for output values. If a binary encoding is
-- used, it is possible that a more compact and sometimes faster state-machine
-- can be built using the Mealy method however this is not always true and not
-- easy to determine without knowing more specifics of the state-machine.
原文：http://www.cnblogs.com/liyusnoopy/p/4873542.html